The present invention relates generally to processing systems and more particularly to a method and apparatus for improving concurrency between processing entities of processing systems.
A computer is known to include a central processing unit, system memory, video graphics circuitry, audio processing circuitry, and peripheral ports. The peripheral ports allow the computer to interface with peripheral devices such as printers, monitors, external tape drives, Internet, etc. In such a computer, the central processing unit functions as a host processor while the video graphics circuit functions as a loosely coupled co-processor. In general, the host processor executes applications and, during execution, calls upon the co-processor to execute its particular function. For example, if the host central processing unit requires a drawing operation to be done, it requests, via a command through a command delivery system, the video graphics co-processor to perform the drawing function.
In many situations, the host central processing unit needs to know the current status of the co-processor, or co-processors, before it can continue with processing the particular application and/or before sending new commands to the co-processor. The host central processing unit obtains such status information from the co-processors via a handshaking protocol. In essence, the hosts central processing initiates the handshaking protocol by polling a co-processor to obtain its status and/or by polling a co-processor register to obtain the stored status. The host processor then determines whether the co-processors status has changed. If so, the host processor updates the co-processor register and continues with additional processing operations. If not, the host processor waits unit the co-processor has completed the current task. Such a technique is known as poll and register writes.
When the host central processing unit continues with processing a particular operation and sending new commands to the co-processor, the processing and sending is done through a buffer. The host central processing unit writes application data and operating instructions into the buffer for the co-processor to read. When the buffer becomes full, the host central processing unit must wait for the co-processor to read the portion of the application data and operating instructions contained in a data block of the buffer before it can resume writing to an empty data block within the buffer.
As such, concurrency between the host central processing unit and the co-processor is reduced. By requiring the host central processing unit to continually check the co-processors progress before it can continue with processing a particular operation and sending new commands to the co-processor, the host central processing unit and co-processor""s operations are interdependent.
Therefore, a need exists for a method and apparatus for processing data with improved concurrency.